Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits
نویسندگان
چکیده
منابع مشابه
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on ...
متن کاملEstimation of Standby Leakage Power in CMOS Circuits
| Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transi...
متن کاملLeakage Power Reduction in Cmos Circuits Using Leakage Control Transistor Technique in Nanoscale Technology
In this paper, we propose a leakage reduction technique. Because high leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits. Sub threshold leakage current plays a very important role in power dissipation. So to reduce the sub threshold leakage current we proposed an adaptive voltage level (AVL) technique. Which optimize the overa...
متن کاملLeakage Power Reduction in Cmos Circuits Using Leakage Control Transistor Technique in Nanoscale Technology
In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage c...
متن کاملTechniques for Leakage Power Reduction in Nanoscale Circuits: A Survey
This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated. 1 The work behind this re...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2010
ISSN: 0975-8887
DOI: 10.5120/1162-1467